Job Details

A company is looking for a Senior ASIC Design Engineer.Key Responsibilities:Implement RTL designs using Verilog/System Verilog for high-speed data paths and packet processing logicCollaborate with verification engineers to create block- and system-level test plans to ensure comprehensive design coverageSupport post-silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issuesMinimum Qualifications:B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or related field8+ years of post-college experience in digital design with proficiency in Verilog and System VerilogExperience in RTL design for high-speed data paths or packet processing in ASICsDeep understanding of Host Ethernet adaptor architecturesFamiliarity with timing closure and modern physical design methodologies